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cy7c1328g 4-mbit (256 k 18) pipelined dcd sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05523 rev. *h revised august 24, 2011 4-mbit (256 k 18) pipelined dcd sync sram features registered inputs and outputs for pipelined operation optimal for performance (double-cycle deselect) ? depth expansion without wait state 256 k 18 common i/o architecture 3.3 v core power supply (v dd ) 3.3 v/2.5 v i/o power supply (v ddq ) fast clock-to-output times ? 2.6 ns (for 250-mhz device) provide high-performance 3-1-1-1 access rate user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed writes asynchronous output enable available in pb-free 100-pin tqfp package ?zz? sleep mode option functional description the cy7c1328g [1] sram integrates 256 k 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inpu ts include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw [a:b] , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin definitions on page 5 and truth table on page 8 for further details). write cycl es can be one to two bytes wide as controlled by the byte write control inputs. gw active low causes all bytes to be writte n. this device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycl e when a deselect is executed. this feature allows depth ex pansion without penalizing system performance. the cy7c1328g operates from a +3.3 v core power supply while all outputs operate with a +3.3 v or a +2.5 v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. note 1. for best practices recommendations, refer to sram system design guidelines . selection guide description 250 mhz 200 mhz 167 mhz 133 mhz unit maximum access time 2.6 2.8 3.5 4.0 ns maximum operating current 325 265 240 225 ma maximum cmos standby current 40 40 40 40 ma [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 2 of 20 address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b byte write register dq a , dqp a byte write register enable register oe sense amps memory array adsp 2 a [1:0] mode ce 2 ce 3 gw bwe pipelined enable dq s, dqp a dqp b output registers input registers e output buffers dq b , dqp b byte write driver dq a, dqp a byte write driver sleep control zz a0, a1, a functional block diagram [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 3 of 20 contents selection guide ................................................................ 4 pin configurations ........................................................... 4 pin definitions .................................................................. 5 functional overview ........................................................ 6 single read accesses ................................................ 6 single write accesses initia ted by adsp ................... 6 single write accesses initiate d by adsc ................... 6 burst sequences ......................................................... 7 sleep mode ................................................................. 7 interleaved burst address table (mode = floating or vdd) ............................................... 7 linear burst address table (mode = gnd) .................. 7 zz mode electrical characteris tics ................................. 7 truth table ....................................................................... 8 truth table for read/write .............................................. 8 maximum ratings ............................................................. 9 operating range ............................................................... 9 electrical characteristics ................................................. 9 capacitance .................................................................... 10 thermal characteristics ................................................. 10 ac test loads and waveforms ..................................... 10 switching characteristics .............................................. 11 switching waveforms .................................................... 12 read timing .............. .............. ............... ........... ........ 12 write timing .............................................................. 13 read/write timing ... .............. .............. .............. ........ 14 zz mode timing ........................................................ 15 ordering information ...................................................... 16 ordering code definitions ..... .................................... 16 package diagram ............................................................ 17 acronyms ........................................................................ 18 document conventions ................................................. 18 units of measure ....................................................... 18 document history page ................................................. 19 sales, solutions, and legal information ...................... 20 worldwide sales and design s upport ......... .............. 20 products .................................................................... 20 psoc solutions ......................................................... 20 [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 4 of 20 pin configurations figure 1. 100-pin tqfp a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1328g nc a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a mode byte a byte b [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 5 of 20 pin definitions pin tqfp type description a 0 , a 1 , a 37,36,32,33, 34,35,44,45, 46,47,48,49, 50,80,81,82, 99,100 input- synchronous address inputs used to select one of the 256 k address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] are fed to the two-bit counter. bw a bw b 93,94 input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw 88 input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all by tes are written, regardless of the values on bw [a:b] and bwe ). bwe 87 input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk 89 input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 98 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 97 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 92 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/desel ect the device. ce 3 is sampled only when a new external address is loaded. oe 86 input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, dq pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automati cally increments the address in a burst cycle. adsp 84 input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presente d to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc 85 input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presente d to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz 64 input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? c ondition with data integrity preserved. during normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs dqp [a:b] 58,59,62,63, 68,69,72,73, 74,8,9,12,13, 18,19,22,23, 24 i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by th e addresses presented during the previous clock rise of the read cycle. the dire ction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp [a:b] are placed in a tristate condition. v dd 15,41,65,91 power supply power supply inputs to the core of the device . v ss 17,40,67,90 ground ground for the core of the device . v ddq 4,11,20,27, 54,61,70,77 i/o power supply power supply for the i/o circuitry . v ssq 5,10,21,26, 55,60,71,76 i/o ground ground for the i/o circuitry . [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 6 of 20 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. the cy7c1328g supports seconda ry cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for proces sors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw [a:b] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. synchronous chip selects ce 1 , ce 2 , ce 3 and an asynchronous output enable (oe ) provide for easy bank selection and output tristate control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always tri-stated during the fi rst cycle of the access. after the first cycle of the access, the ou tputs are controlled by the oe signal. consecutive single read cycles are supported. the cy7c1328g is a double-cycl e deselect part. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will tristate immediately after the next clock rise. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) chip select is asserted active. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the write signals (gw , bwe , and bw [a:b] ) and adv inputs are ignored during this first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dqx inputs is written into the corresponding address location in the memory core. if gw is high, then the write operation is controlled by bwe and bw [a:b] signals. the cy7c1328g provides byte write capability that is described in the write cycle description table. asserting the byte write enable input (bwe ) with the selected byte write input will selectively write to only the de sired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write me chanism has been provided to simplify the write operations. because the cy7c1328g is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so will tristate the output drivers. as a safety precaution, dq are automatically tri-stated whenever a write cycle is detected, rega rdless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is assert ed active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw [a:b] ) are asserted active to conduct a wr ite to the desired byte(s). adsc triggered write accesse s require a single clock cycle to complete. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the adv input is ignored du ring this cycle. if a global write is conducted, the data presented to the dq x is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronou s self-timed write mechanism has been provided to simplify the write operations. because the cy7c1328g is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq x inputs. doing so will trista te the output drivers. as a safety precaution, dq x are automatically tri-stated whenever a write cycle is detected, rega rdless of the state of oe . mode 31 input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc 1,2,3,6,7,14, 16,25,28,29, 30,38,39,42, 43,51,52,53, 56,57,66,75, 78,79,95,96 no connects . not internally connected to the die. pin definitions (continued) pin tqfp type description [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 7 of 20 burst sequences the cy7c1328g provides a two- bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to s upport processors that follow a linear burst sequence. the burs t sequence is user selectable through the mode input. both read and write burst operations are supported. asserting adv low at clock rise will au tomatically increment the burst counter to the next addre ss in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the o peration guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz snooze mode standby current zz > v dd ? 0.2 v ? 40 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to snooze current this parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit snooze current this parameter is sampled 0 ? ns [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 8 of 20 truth table the truth table for part cy7c1328g is as follows. [2, 3, 4, 5, 6] operation address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselected cycle, power-dow n none h x x l x l x x x l-h tristate deselected cycle, power-dow n none l l x l l x x x x l-h tristate deselected cycle, power-dow n none l x h l l x x x x l-h tristate deselected cycle, power-dow n none l l x l h l x x x l-h tristate deselected cycle, power-dow n none l x h l h l x x x l-h tristate zz mode, power-down none x x x h x x x x x x tristate read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tristate write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tristate read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tristate read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tristate write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tristate read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tristate write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d truth table for read/write the truth table for read or write for part cy7c1328g is as follows. [2] function gw bwe bw a bw b read h h x x read h l h h write byte a - (dq a and dqp a )hllh write byte b - (dq b and dqp b )hlhl write all bytes h l l l write all bytes l x x x notes 2. x = ?don't care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals (bw a , bw b ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b ), bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur onl y on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tristate. oe is a don't care for the remai nder of the write cycle. 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tristate when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low). [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 9 of 20 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature... ............... ............... ?65 c to +150 c ambient temperature with power applied ............. ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd ........?0.5 v to +4.6 v supply voltage on v ddq relative to gnd....... ?0.5 v to +v dd dc voltage applied to outputs in tristate ............................................?0.5 v to v ddq + 0.5 v dc input voltage .................................. ?0.5 v to v dd + 0.5 v current into outputs (low) ......................................... 20 ma static discharge voltage........................................... > 2001 v (per mil-std-883, method 3015) latch up current...................................................... > 200 ma operating range range ambient temperature (t a ) v dd v ddq commercial 0 c to +70 c 3.3 v ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range [7, 8] parameter description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage v ddq = 3.3 v, v dd = min, i oh = ?4.0 ma 2.4 ? v v ddq = 2.5 v, v dd = min, i oh = ?1.0 ma 2.0 ? v v ol output low voltage v ddq = 3.3 v, v dd = max, i ol = 8.0 ma ? 0.4 v v ddq = 2.5 v, v dd = max, i ol = 1.0 ma ? 0.4 v v ih input high voltage [7] v ddq = 3.3 v 2.0 v dd + 0.3 v v v ddq = 2.5 v 1.7 v dd + 0.3 v v v il input low voltage [7] v ddq = 3.3 v ?0.3 0.8 v v ddq = 2.5 v ?0.3 0.7 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5a input current of zz input = v ss ?5 ? a input = v dd ?30a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz ? 325 ma 5-ns cycle, 200 mhz ? 265 ma 6-ns cycle, 167 mhz ? 240 ma 7.5-ns cycle, 133 mhz ? 225 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = f max = 1/t cyc 4-ns cycle, 250 mhz ? 120 ma 5-ns cycle, 200 mhz ? 110 ma 6-ns cycle, 167 mhz ? 100 ma 7.5-ns cycle, 133 mhz ? 90 ma notes 7. overshoot: v ih (ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 2 v (pulse width less than t cyc /2). 8. t power-up : assumes a linear ramp from 0 v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd. [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 10 of 20 note 9. tested initially and after any design or process change that may affect these parameters. i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 40 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc 4-ns cycle, 250 mhz ? 105 ma 5-ns cycle, 200 mhz ? 95 ma 6-ns cycle, 167 mhz ? 85 ma 7.5-ns cycle, 133 mhz ? 75 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = 0 all speeds ? 45 ma capacitance [9] parameter description test conditions 100 tqfp max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v v ddq = 3.3 v 5pf c clk clock input capacitance 5 pf c i/o input/output capacitance 5 pf thermal characteristics [9] parameter description test conditions 100 tqfp package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 30.32 c/w jc thermal resistance (jun ction to case) 6.85 c/w ac test loads and waveforms electrical characteristics over the operating range [7, 8] (continued) parameter description test conditions min max unit output r = 317 r = 351 5pf including jig and scope (a) (b) output r l = 50 z 0 = 50 v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r = 1667 r =1538 5pf including jig and scope (a) (b) output r l = 50 z 0 = 50 v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 11 of 20 switching characteristics over the operating range [10, 11, 12, 13, 14, 15] parameter description ?250 ?200 ?167 ?133 unit min max min max min max min max t power v dd (typical) to the first access [12] 1.0 ? 1.0 ? 1.0 ? 1.0 ? ms clock t cyc clock cycle time 4.0 ? 5.0 ? 6.0 ? 7.5 ? ns t ch clock high 1.7 ? 2.0 ? 2.5 ? 3.0 ? ns t cl clock low 1.7 ? 2.0 ? 2.5 ? 3.0 ? ns output times t co data output valid after clk rise ? 2.6 ? 2.8 ? 3.5 ? 4.0 ns t doh data output hold after clk rise 1.0 ? 1.0 ? 1.5 ? 1.5 ? ns t clz clock to low z [13, 14, 15] 0 ? 0 ? 0 ? 0 ? ns t chz clock to high z [13, 14, 15] ? 2.6 ? 2.8 ? 3.5 ? 4.0 ns t oev oe low to output valid ? 2.6 ? 2.8 ? 3.5 ? 4.0 ns t oelz oe low to output low z [13, 14, 15] 0 ? 0 ? 0 ? 0 ? ns t oehz oe high to output high z [13, 14, 15] ? 2.6 ? 2.8 ? 3.5 ? 4.0 ns setup times t as address setup be fore clk rise 1.2 ? 1.2 ? 1.5 ? 1.5 ? ns t ads adsc , adsp setup before clk rise 1.2 ? 1.2 ? 1.5 ? 1.5 ? ns t advs adv setup before clk rise 1.2 ? 1.2 ? 1.5 ? 1.5 ? ns t wes gw , bwe , bw x setup before clk rise 1.2 ? 1.2 ? 1.5 ? 1.5 ? ns t ds data input setup before clk rise 1.2 ? 1.2 ? 1.5 ? 1.5 ? ns t ces chip enable setup before clk rise 1.2 ? 1.2 ? 1.5 ? 1.5 ? ns hold times t ah address hold after clk rise 0.3 ? 0.5 ? 0.5 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.3 ? 0.5 ? 0.5 ? 0.5 ? ns t advh adv hold after clk rise 0.3 ? 0.5 ? 0.5 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.3 ? 0.5 ? 0.5 ? 0.5 ? ns t dh data input hold after clk rise 0.3 ? 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.3 ? 0.5 ? 0.5 ? 0.5 ? ns notes 10. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 11. test conditions shown in (a) of ac test loads unless otherwise noted. 12. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 13. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 14. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect paramete rs guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system conditions. 15. this parameter is sampled and not 100% tested. [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 12 of 20 switching waveforms read timing [16] note 16. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe,bw data out (dq) high-z t doh t co adv t oehz t co single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address adv suspends burst don?t care undefined [a:b] clz t [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 13 of 20 write timing [17, 18] notes 17. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 18. full width write can be initiated by either gw low; or by gw high, bwe low and bw [a:b] low. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw [a :b] data out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 14 of 20 read/write timing [19, 20, 21] notes 19. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 20. the data bus (q) remains in high z following a write cycle, unless a new read access is initiated by adsp or adsc . 21. gw is high. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw [a:b] data out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3 [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 15 of 20 zz mode timing [22, 23] notes 22. device must be deselected when entering zz mode. see truth t able for all possible signal conditions to deselect the device. 23. dqs are in high z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec all inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 16 of 20 ordering information cypress offers other versions of this type of product in many different configurations and features. the following table contai ns only the list of parts that are currently available. for a complete listing of all optio ns, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices . speed (mhz) ordering code package diagram package type operating range 133 CY7C1328G-133AXI 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free industrial ordering code definitions temperature range: i = industrial package type: ax = 100-pin tqfp (pb-free) speed grade (133 mhz) process technology 90 nm 1328 = dcd, 256 k 18 (4 mb) cy7c = cypress srams cy7c 1328 g - 133 i ax [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 17 of 20 package diagram figure 2. 100-pin tqfp (14 20 1.4 mm), 51-85050 51-85050 *d [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 18 of 20 acronyms document conventions units of measure acronym description ce chip enable cen clock enable i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack we write enable symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes ms milli seconds mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback
cy7c1328g document number: 38-05523 rev. *h page 19 of 20 document history page document title: cy7c1328g 4-mbit (256 k 18) pipelined dcd sync sram document number: 38-05523 rev. ecn no. issue date orig. of change description of change ** 224371 see ecn rkf new data sheet *a 288909 see ecn vbl changed tqfp to pb-free tqfp in ordering information section *b 333625 see ecn syt removed 133-mhz speed grade changed 166-mhz to 167-mhz speed bin changed the test condition from v dd = min. to v dd = max. for v ol in the electrical characteristics table replaced tbds for ja and jc to their respective values on the thermal resistance table *c 419264 see ecn rxu converted from preliminary to final changed address of cypress semiconducto r corporation on page# 1 from ?3901 north first street? to ?198 champion court? modified test condition from v ih < v dd to v ih < v dd modified ?input load? to ?input leakage current except zz and mode? in the electrical characteristics table replaced package name column with package diagram in the ordering information table replaced package diagram of 51-85050 from *a to *b updated the ordering information *d 430373 see ecn nxr include 133-mhz speed grade updated the ordering information *e 480368 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd. updated the ordering information table. *f 2896584 03/20/2010 njy removed obsolete part num bers from ordering information table and updated package diagrams. *g 3045943 10/03/2010 njy added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. *h 3353361 prit 08/24/2011 updated 100-pin tqfp package diagram. modified note 1 on page 1. [+] feedback
document number: 38-05523 rev. *h revised august 24, 2011 page 20 of 20 intel and pentium are registered trademarks, and i486 is a trademark, of intel corporation. powerpc is a registered trademark o f ibm. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1328g ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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